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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM62486B/D
32K x 9 Bit BurstRAMTM Synchronous Static RAM
With Burst Counter and Self-Timed Write
The MCM62486B is a 294,912 bit synchronous static random access memory designed to provide a burstable, high-performance, secondary cache for the i486 and PentiumTM microprocessors. It is organized as 32,768 words of 9 bits, fabricated with Motorola's high-performance silicon-gate CMOS technology. The device integrates input registers, a 2-bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 - A14), data inputs (D0 - D8), and all control signals except output enable (G) are clock (K) controlled through positive-edge-triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM62486B (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. The MCM62486B will be available in a 44-pin plastic leaded chip carrier (PLCC). Multiple power and ground pins have been utilized to minimize effects induced by output noise. Separate power and ground pins have been employed for DQ0 - DQ8 to allow user-controlled output levels of 5 volts or 3.3 volts. * Single 5 V 10% Power Supply ( 5% for MCM62486BFN11) * Choice of 5 V or 3.3 V 10% Power Supplies for Output Level Compatibility * Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min * Internal Input Registers (Address, Data, Control) * Internally Self-Timed Write Cycle * ADSP, ADSC, and ADV Burst Control Pins * Asynchronous Output Enable Controlled Three-State Outputs * Common Data Inputs and Data Outputs * High Output Drive Capability: 85 pF per I/O * High Board Density PLCC Package * Fully TTL-Compatible * Active High and Low Chip Select Inputs for Easy Depth Expansion
MCM62486B
FN PACKAGE 44-LEAD PLCC CASE 777-01
PIN ASSIGNMENT
A1 A0 ADV ADSC ADSP K V CC A7 A8 A9 A10 A2 A3 A4 A5 A6 VSS DQ0 DQ1 VSSQ VCCQ DQ2 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 11 35 12 34 33 13 32 14 15 31 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 DQ3 V SSQ V SS W V CC V SS G S0 S1 DQ8 V SSQ A11 A12 A13 A14 VSS DQ7 DQ6 VSSQ VCCQ DQ5 DQ4
PIN NAMES
A0 - A14 . . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable S0, S1 . . . . . . . . . . . . . . . . . . . . Chip Selects ADV . . . . . . . . . . . . Burst Address Advance ADSP, ADSC . . . . . . . . . . . . Address Status DQ0 - DQ8 . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VCCQ . . . . . . . Output Buffer Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground VSSQ . . . . . . . . . . . . Output Buffer Ground All power supply and ground pins must be connected for proper operation of the device. VCC VCCQ at all times including power up.
BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp.
REV 2 5/95
(c) Motorola, Inc. 1994 MOTOROLA FAST SRAM
MCM62486B 1
BLOCK DIAGRAM (See Note)
ADV BURST LOGIC Q0 BINARY COUNTER K A0 15 Q1 A1 A1 INTERNAL A0 ADDRESS 32K x 9 MEMORY ARRAY
ADSC ADSP
CLR
2 A0 - A14 ADDRESS REGISTER 15 A1 - A0 A2 - A14 9 9
W
WRITE REGISTER
DATA-IN REGISTERS
S0 S1 G DQ0 - DQ8 9
ENABLE REGISTER
OUTPUT BUFFER
NOTE: All registers are positive-edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip selects (S0, S1) are sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE.
BURST SEQUENCE TABLE (See Note)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A14 - A2 A14 - A2 A14 - A2 A14 - A2 A1 A1 A1 A1 A0 A0 A0 A0
NOTE: The burst wraps around to its initial state upon completion.
MCM62486B 2
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)
S F F T T T X X X X ADSP L X L H H H H H H ADSC X L X L L H H H H ADV X X X X X L L H H W X X X L H L H L H K L-H L-H L-H L-H L-H L-H L-H L-H L-H Address Used N/A N/A External Address External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K). 3. S represents S0 and S1. T implies S1 = L and S0 = H; F implies S1 = H or S0 = L. 4. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected G L H X X I/O Status Data Out (DQ0 - DQ8) High-Z High-Z -- Data In (DQ0 - DQ8) High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0)
Rating Power Supply Voltage Output Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC VCCQ Vin, Vout Iout PD Tbias TA Value - 0.5 to 7.0 - 0.5 to VCC - 0.5 to VCC + 0.5 20 1.0 - 10 to + 85 0 to + 70 Unit V V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.
Storage Temperature Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
MCM62486B 3
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC, VCCQ = 5.0 V 5%, TA = 0 to + 70C, for device MCM62486B-11) (VCC = 5.0 V 10%, VCCQ = 5.0 V or 3.3 V 10%, TA = 0 to + 70C, for all other devices) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Output Buffer Supply Voltage (5.0 V TTL Compatible) (3.3 V 50 Compatible) Input High Voltage Input Low Voltage * VIL (min) = - 3.0 V ac (pulse width 20 ns) Symbol VCC VCCQ 4.5 3.0 VIH VIL 2.2 - 0.5* 5.5 3.6 VCC + 0.3 0.8 V V Min 4.5 Max 5.5 Unit V V
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G, S1 = VIH, S0 = VIL, Vout = 0 to VCCQ) AC Supply Current (G, S1 = VIL, S0 = VIH, All Inputs = VIL = 0.0 V and VIH 3.0 V, Iout = 0 mA, Cycle Time tKHKH min) Standby Current (S1 = VIH, S0 = VIL, All Inputs = VIL and VIH, Cycle Time tKHKH min) Output Low Voltage (IOL = + 8.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA ISB1 VOL Min -- -- -- -- -- Max 1.0 1.0 160 50 0.4 Unit A A mA mA V
Output High Voltage (IOH = - 4.0 mA) VOH 2.4 -- V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance (All Pins Except DQ0 - DQ8) Input/Output Capacitance (DQ0 - DQ8) Symbol Cin CI/O Typ 2 7 Max 3 8 Unit pF pF
MCM62486B 4
MOTOROLA FAST SRAM
(VCC, VCCQ = 5.0 V 5%, TA = 0 to + 70C, for device MCM62486B-11) (VCC = 5.0 V 10%, VCCQ = 5.0 V or 3.3 V 10%, TA = 0 to + 70C, for all other devices)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
AC OPERATING CONDITIONS AND CHARACTERISTICS
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
62486B-11 Parameter Cycle Time Clock Access Time Output Enable Access Clock High to Output Active Clock High to Q Change Output Enable to Q Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address Address Status Data In Write Address Advance Chip Select Address Address Status Data In Write Address Advance Chip Select Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tADSVKH tDVKH tWVKH tADVVKH tS0VKH tS1VKH tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHS0X tKHS1X Min 15 -- -- 6 3 0 -- -- 5.5 5.5 2 Max -- 11 5 -- -- -- 6 6 -- -- -- 62486B-12 Min 20 -- -- 6 3 0 -- -- 7 7 2 Max -- 12 5 -- -- -- 6 6 -- -- -- 62486B-14 Min 20 -- -- 6 4 0 -- -- 8 8 3 Max -- 14 6 -- -- -- 6 6 -- -- -- 62486B-19 Min 25 -- -- 6 4 0 -- -- 6 6 3 Max -- 19 7 -- -- -- 7 6 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 5 4 Notes
Hold Times:
2
--
2
--
2
--
2
--
ns
5
NOTES: 1. A read cycle is defined by W high or ADSP low for the setup and hold times. A write cycle is defined by W low and ADSP high for the setup and hold times. 2. All read and write cycle timings are referenced from K or G. 3. G is a don't care when W is sampled low. 4. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever ADSP and ADSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is selected.Chip select must be true (S1 low and S0 high) at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled. Timings for S1 and S0 are similar.
AC TEST LOADS
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V OUTPUT 255 5 pF 480
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM62486B 5
READ CYCLES
t KHKH
MCM62486B 6
t KHKL t KLKH t KHADSX t ADSVKH t KHAX A1 t KHWX t WVKH A2 t KHS1X t KHADVX t ADVVKH t KHQV t GLQV (ADV SUSPENDS BURST) t GHQZ Q(A1) SINGLE READ t KHQX2 Q(A2) t KHQV Q(A2+1) Q(A2+2) BURST READ (BURST WRAPS AROUND TO ITS INITIAL STATE) Q(A2+3) Q(A2) Q(A2+1) t KHQZ
t KHADSX
K
t ADSVKH
ADSP
ADSC
t AVKH
ADDRESS
W
t S1VKH
S1 (S0 = VIH)
ADV
G
t GLQX
DATA OUT
Q(A2+2)
MOTOROLA FAST SRAM
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2+1) represents the next output data in the burst sequence with A2 as the base address.
WRITE CYCLES
t KHKH
K t KLKH t KHKL t KHADSX
t ADSVKH
MOTOROLA FAST SRAM
t ADSVKH t KHADSX ADSC STARTS NEW BURST t KHAX A1 W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST A2 A3 t KHWX t WVKH t KHSOX t ADVVKH ADV SUSPENDS BURST t DVKH D(A) t GHQZ D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) t KHDX SINGLE WRITE BURST WRITE (WITH A SUSPENDED CYCLE) NEW BURST WRITE
ADSP
ADSC
t AVKH
ADDRESS
W
t SOVKH
S0 (S1 = VIL ) t KHADVX
ADV
G
DATA IN
D(A3+2)
DATA OUT
Q(An-1)
Q(An)
MCM62486B 7
BURST READ
MCM62486B 8
COMBINATION READ/WRITE CYCLE (E low, ADSC high)
t KHKH t ADSVKH t KHADSX t KHKL t KLKH t AVKH A1 A2 A3 t KHAX t WVKH t KHWX t ADVVKH t KHADVX t KHQV t DVKH D(A2) t KHQX1 Q(A1) READ WRITE t GHQZ t GLQX Q(A3) t KHQX2 t KHDX t GLQV Q(A3+1) BURST READ Q(A3+2)
K
ADSP
ADDRESS
W
ADV
G
DATA IN
MOTOROLA FAST SRAM
DATA OUT
APPLICATION EXAMPLE
DATA BUS DATA ADDRESS BUS ADDRESS 15 CLOCK i486DX4 36
ADDR CLK K CACHE CONTROL LOGIC
ADDR K ADSC W G ADV
DATA
MCM62486B
ADSP
ADS CONTROL
128K Byte Burstable, Secondary Cache Using 4 MCM62486BFN19s With a 100 MHz i486DX4
MOTOROLA FAST SRAM
MCM62486B 9
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
62486B
XX
XX
Speed (11 = 11 ns, 12 = 12 ns, 14 = 14 ns, 19 = 19 ns) Package (FN = PLCC)
Full Part Numbers -- MCM62486BFN11
MCM62486BFN12
MCM62486BFN14
MCM62486BFN19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM62486B 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE 44-LEAD PLCC CASE 777-02 -NY BRK D -L44 LEADS ACTUAL -MW D V A Z R 0.18 (0.007)
M
B
0.18 (0.007) U
M
T L -M
M
S
N
S S
0.18 (0.007)
T L -M
N
S
Z
44
1
0.18 (0.007)
M
T L -M
S
N
S
X VIEW D-D
G1 0.25 (0.010)
S
T L -M
S
N
S
T L -M
S
N
S
H C E 0.10 (0.004) G G1 0.25 (0.010) S T L -M J VIEW S
S
0.18 (0.007)
M
T L -M
S
N
S
K1 K F VIEW S 0.18 (0.007)
M
-T-
SEATING PLANE
T L -M
S
N
S
N
S
NOTES: 1. DUE TO SPACE LIMITATION, CASE 777-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 44 LEADS. 2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.25 (0.010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO .012 (.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN .037 (.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN .025 (.635). 9. 777-01 IS OBSOLETE, NEW STANDARD 777-02.
DIM A B C E F G H J K R U V W X Y Z G1 K1
MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 -- 0.64 -- 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 -- 0.50 2 10 15.50 16.00 1.02 --
INCHES MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 -- 0.025 -- 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 -- 0.020 2 10 0.610 0.630 0.040 --
MOTOROLA FAST SRAM
MCM62486B 11
Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM62486B 12
*MCM62486B/D*
MCM62486B/D MOTOROLA FAST SRAM

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